เรื่องที่ 3 ไม่ทราบว่าเคยลองทดสอบไหมครับว่า ระหว่าง MS Windows vs Apple OSX ใช้โปรแกรมเดียวกัน (เอาเป็น iTunes แล้วกัน) บนเครื่องเดียวกัน แล้วส่งสัญญาณเสียงแบบ digital -> usb -> dac นั้นให้ความรู้สึกของเพลงที่แตกต่างกันหรือไม่?
ขอบคุณครับ
เรื่อง 1-2 นั้นเป็นข้อมูลเพื่อหา DAC มาใช้งานบ้าง
เรื่อง 3 นี้ถ้าความรู้สึกของเพลงต่างนี้นั้นแสดงว่า OS ก็มีผลกับการ process ด้วยนอกจากโปรแกรม player
FEATURES
Designed for Signaling Rates up to 1.65 Gbps in Support of UXGA Display
Differential Interface Compatible with Transition Minimized Differential Signaling (TMDS) Electrical Specification
Each Port Supports HDMI or DVI Inputs
Isolated Digital Display Control (DDC) Bus for Unused Ports
5-V Tolerance to all DDC and HPD_SINK Inputs
Integrated Receiver Termination
Inter-Pair Output Skew < 100 ps
8-dB Receiver Equalization to Compensate for 5-m DVI Cable Losses
High Impedance Outputs When Disabled
HBM ESD Protection Exceeds 3 kV
3.3-V Supply Operation
APPLICATIONS
Switching From Three Digital-Video (DVI) or Digital-Audio Visual (HDMI) Sources
Digital TV
Digital Projector
Audio Video Receiver
DESCRIPTION
The TMDS341 is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to 3 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug detector, and an I2C interface are supported on each port. Each TMDS channel allows signaling rates up to 1.65 Gbps.
The active source is selected by configuring source selectors, S1, S2, and S3. The selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I2C interface of the selected input port is linked to the I2C interface of the output port, and the hot plug detector (HPD) of the selected input port is output to
HPD_SINK. For the unused ports, the I2C interfaces are isolated, and the HPD pins are kept low.
Termination resistors (50-W), pulled up to VCC, are integrated at each receiver input pin. External terminations are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard. When the output is connected to a standard TMDS termination and OE is high, the output is high impedance.
The TMDS341 provides fixed 8-dB input equalization and selectable 3-dB output de-emphasis to optimize system performance through 5-meter or longer DVI compliant cables. The device is characterized for operation from 0C to 70C.
สัญญาณอินพุท D+ D- จากUSB Port
หน้า26 USB Host Interface Sequence
- Power-On, Attach, and Playback Sequence
The PCM2704/5/6/7 is ready for setup when the reset sequence has finished and the USB bus is attached. After a connection has been established by setup, the PCM2704/5/6/7 is ready to accept USB audio data. While waiting for the audio data (idle state), the analog output is set to bipolar zero (BPZ). When receiving the audio data, the PCM2704/5/6/7 stores the first audio packet, which contains 1 ms of audio data, into the internal storage buffer. The PCM2704/5/6/7 starts playing the audio data after detecting the next subsequent start-of-frame (SOF) packet.
- Play, Stop, and Detach Sequence
When the host finishes or aborts the playback, the PCM2704/5/6/7 stops playing after completing the output of the last audio data.
- Suspend and Resume Sequence
The PCM2704/5/6/7 enters the suspend state after the USB bus has been in a constant idle state for approximately 5 ms. While the PCM2704/5/6/7 is in the suspend state, SSPND flag (pin 27 for PCM2704/5, pin 11 for PCM2706/7) is asserted. The PCM2704/5/6/7 wakes up immediately when detecting the non-idle state on the USB bus.
หน้า17 USB Audio Function Topology
- Interface #0 (Default/Control Interface)
Interface #0 is the control interface. Setting #0 is the only possible setting for interface #0. Setting #0 describes the standard audio control interface. Audio control interface consists of a terminal. The PCM2704/5/6/7 has three terminals:
Input terminal (IT #1) for isochronous-out stream
Output terminal (OT #2) for audio analog output
Feature unit (FU #3) for DAC digital attenuator
- Interface #2 (HID Interface)
Interface #2 is the interrupt-data-in interface. Interface #2 comprises the HID consumer control device. Alternative setting #0 is the only possible setting for interface #2.
On the HID device descriptor, eight HID items are reported as follows for any model, in any configuration.
- Basic HID Operation
Interface #2 can report the following three key statuses for any model. These statuses can be set by the HID0HID2 pins (PCM2704/6) or the SPI port (PCM2705/7).
Mute (0xE2)
Volume up (0xE9)
Volume down (0xEA)
- Extended HID Operation (PCM2705/6/7)
By using the FUNC0FUNC3 pins (PCM2706) or the SPI port (PCM2705/7), the following additional conditions can be reported to the host.
Play/Pause (0xCD)
Stop (0xB7)
Previous (0xB6)
Next (0xB5)
- Auxiliary HID Status Report (PCM2705/7)
One additional HID status can be reported to the host though the SPI port. This status flag is defined by SPI command or external ROM. This definition must be described as on the report descriptor with a three-byte usage ID. AL A/V Capture (0x0193) is assigned as the default for this status flag.
- Endpoints
The PCM2704/5/6/7 has three endpoints:
Control endpoint (EP #0)
Isochronous-out audio data-stream endpoint (EP #2)
HID endpoint (EP #5)
The control endpoint is a default endpoint. The control endpoint is used to control all functions of the PCM2704/5/6/7 by standard USB request and USB audio-class-specific request from the host. The isochronous-out audio data-stream endpoint is an audio sink endpoint that receives the PCM audio data. The isochronous-out audio data-stream endpoint accepts the adaptive transfer mode. The HID endpoint is an interrupt-in endpoint. The HID endpoint reports HID status every 10 ms.
The HID endpoint is defined as a consumer-control device. The HID function is designed as an independent endpoint from the isochronous-out endpoint. This means that the effect of HID operation depends on host software. Typically, the HID function is used to control the primary audio-out device.
สัญญาณ S/PDIF , I2S I/F ภายในตัวPCM2706
หน้า19 - หน้า20 DAC
The PCM2704/5/6/7 has a DAC that uses an oversampling technique with 128-fS second-order multibit noise shaping. This technique provides extremely low quantization noise in the audio band, and the built-in analog low-pass filter removes the high-frequency components of the noise-shaping signal. DAC outputs through the headphone amplifier VOUTL and VOUTR can provide 12 mW at 32 Ω, as well as 1.8 VPP into a 10-kΩ load.
Digital Audio InterfaceS/PDIF Output
The PCM2704/5/6/7 employs S/PDIF output. Isochronous-out data from the host are encoded to S/PDIF output DOUT, as well as to DAC analog outputs VOUTL and VOUTR. Interface format and timing follow the IEC-60958 standard. Monaural data are converted to the stereo format at the same data rate. S/PDIF output is not supported in the I2S I/F enable mode. The implementation of this feature is optional. Note that it is your responsibility to determin whether to implement this feature in your product or not.
Channel Status Information
The channel status information is fixed as consumer application, PCM mode, copyright, and digital/digital converter. All other bits are fixed as 0s, except for the sample frequency, which is set automatically according to the data received through the USB.
Copyright Management
Digital audio data output always is encoded as original with SCMS control. Only one generation of digital duplication is allowed.
Digital Audio InterfaceI2S Interface Output (PCM2706/7)
The PCM2706 and PCM2707 can support the I2S interface, which is enabled by FSEL (pin 9). In the I2S interface enabled mode, pins 4, 18, 19, 5, and 17 are assigned as DIN, SYSCK, BCK, LRCK, and DOUT, respectively. They provide digital output/input data in the 16-bit I2S format, which also is accepted by the internal DAC. I2S interface format and timing are shown in Figure 22, Figure 23, and Figure 24.
หน้า21 External ROM Descriptor (PCM2704/6)
The PCM2704/6 supports an external ROM interface to override internal descriptors. Pin 3 (for PCM2704)/pin 15 (for PCM2706) is assigned as DT (serial data) and pin 2 (for PCM2704)/pin 14 (for PCM2706) is assigned as CK (serial clock) of the I2C interface when using the external ROM descriptor. Descriptor data is transferred from the external ROM to the PCM2704/6 through the I2C interface the first time when the device activates after power-on
reset. Before completing a read of the external ROM, the PCM2704/6 replies with NACK for any USB command request from the host to the device itself. The descriptor data, which can be in external ROM, are as follows. String descriptors must be described in ANSI ASCII code (1 byte for each character). String descriptors are converted automatically to unicode strings for transmission to the host. The device address of the external ROM is fixed as 0xA0. The data must be stored from address 0x00 and must consist of 57 bytes, as described in the following items. The data bits must be sent from LSB to MSB on the I2C bus. This means that each byte of data must be stored with its bits in reverse order. Read operation is performed at a frequency of XTI/384 (approximately 30 kHz). The content of power attribute and max power must be consistent with actual application circuit configuration (PSEL setting and actual power usage from VBUS of USB connector); otherwise, it may cause improper or unexpected PCM2704/6 operation.
Vendor ID (2 bytes)
Product ID (2 bytes)
Product string (16 bytes in ANSI ASCII code)
Vendor string (32 bytes in ANSI ASCII code)
Power attribute (1 byte)
Max power (1 byte)
Auxiliary HID usage ID in report descriptor (3 bytes)
PCM1744 USB Audio Interface
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หน้า6 SYSTEM CLOCK
The system clock for PCM1744 must be either 256fS or 384fS, where fS is the audio sampling frequency (LRCIN), typically 32kHz, 44.1kHz, 48kHz, 88.2kHz or 96kHz. The system clock is used to operate the digital filter and the noise shaper. The system clock input (SCKI) is at pin 14. Timing conditions for SCKI are shown in Figure 3.
PCM1744 has a system clock detection circuit which automatically detects the frequency, either 256fS or 384fS. The system clock should be synchronized with LRCIN (pin 1), but PCM1744 can compensate for phase differences. If the phase difference between LRCIN and system clock is greater than +-6 bit clocks (BCKIN), the synchronization is performed automatically. The analog outputs are forced to a bipolar zero state (VCC/2) during the synchronization function. Table I shows the typical system clock frequency inputs for the PCM1744.
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