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Originally posted by ssk
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และอีกสองปี เจ็คฮวง คงเอาจริงจังกัดกัน x86
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เรียกว่าเริ่มกัดกิน มานาน
และอีกสองปี เจ็คฮวง คงเอาจริงจังกัดกัน x86 -
https://www.overclockzone.com/TSMC-5...-main-customer
ข่าวจจาก โอเวอร์คล้อกโซน สำหรับ ห้านาโนเมตร TSMC
ผลิตให้ apple ลูกค้ารายหลักก็เหลือแหร่ และ โรงงานซัมซุง Global foundary ควรเร่งพัฒนา
ฝีม้ือแรงงานให้ทันเบอร์ 1 มากกกว่า นี้ X86 ก็ไม่ไรมากทั้งสองบริษัทตามเช็ดใช้โหนดตามก้น
มือถือเค้าไป 55555+
Last edited by micronz; 23 Sep 2020, 02:43:19.Comment
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Arm เปิดตัว N2 กับ V2 สำหรับ SERVER ออกมาอีกแล้วล่ะครับ
สรุปคร่าวๆคือ V1 คือ X1 ของฝั่ง SERVER ซึ่งมีชุดคำสั่ง 256 Bits VECTOR 2 ชุดต่อ CORE เทียบเท่า X86 เกือบทั้งหมด ซึ่งตามข่าวผู้ที่ผลิต CORE ตัวนี้ออกมาขายคือ Ampere ซึ่งเป็น PArtner กับ NVIDIA ในฝั่ง ARM มาก่อน
และเห็นว่า GIGABํYTE เป็นคนทำตัว SERVER MB และ Complete UNIT ให้ อื่นๆอ่านตามข่าวเลยครับ ซึ่งพัฒนาการของ ARM มันข้าม Core เล็กๆ ไปเป็น Core ขนาดใหญ่ทัดเทียมกับ X86 ไปแล้วล่ะครับ
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ARM ฝากบอก INTEL ว่า ผมไม่เล็กแล้วนะครับ
by Andrei Frumusanu on September 22, 2020 9:00 AM EST
Arm’s ambitions for the server market has been a very long journey that’s taken years to materialise. After many doubts and false start attempts, today in 2020 nobody can deny that sever chips powered by the company’s CPU IP are not only competitive, but actually class-leading on several metrics.
Amazon’s Graviton2 64-core Neoverse N1 server chip is the first of what should become a wider range of designs that will be driving the Arm server ecosystem forward and actively assaulting the infrastructure CPU market share that’s currently dominated by the x86 players such as Intel and AMD.
The journey has been a long one, but has had its roots back in roadmaps publicly planned laid out by the company back in 2018. Fast-forward to 2020, not only have we seen products with the first-generation Neoverse N1 infrastructure CPU IP hit the market in commercial and publicly available form, but we’ve seen the company exceed their targeted 30% generational gain by a factor of 2x.
The Neoverse V1: A New Maximum Performance Tier Infrastructure CPU
Today, we’re ready to take the next step towards the next generation of the Neoverse platform, not only revealing the CPU microarchitecture previously known as Zeus, but a whole new product category that goes beyond the Neoverse N-series: Introducing the new Neoverse V-series and the Neoverse V1 (Zeus), as well as a new roadmap insertion in the form of the Neoverse N2 (Perseus).
The new Neoverse V1 introduces the new V-series into Arm’s infrastructure IP portfolio, and essentially this represents the company’s push for higher absolute performance, no matter the cost.
Earlier this spring we covered the company’s new mobile Cortex-X1 CPU IP which represented significant business model change for Arm: Instead of offering only a single one-fits-all CPU microarchitecture which licensees had to make due with in a wider range of designs and performance points, we’ve now seen a divergence of the microarchitectures, with one IP offering now focusing on pure maximum performance (Cortex-X1), no matter the area or power cost, while the other design (Cortex-A78) focuses on Arm’s more traditional maximised PPA (Power, Performance, Area) design philosophy.
The Zeus microarchitecture in the form of the Neoverse V1 is essentially the infrastructure counterpart to what Arm has achieved in the mobile IP offering with the Hera Cortex-X1 CPU IP: A focus on maximum performance, with a lesser regard to power and area.
This means that the V1 has significantly larger caches, cores structures, using up more area and power to achieve unprecedented performance levels.
In terms of generational performance uplift, it’s akin to Arm throwing down the gauntlet to the competition, achieving a ground-breaking +50 IPC boost compared to Neoverse N1 that we’re seeing in silicon today. The performance uplift potential here is tremendous, as this is merely a same-process ISO-frequency upgrade, and actual products based on the V1 will also in all likelihood also see additional performance gains thanks to increased frequencies through process node advancements.
If we take the conservatively clocked Graviton2 with its 2.5GHz N1 cores as a baseline, a theoretical 3GHz V1 chip would represent an 80% uplift in per-core single-threaded performance. Not only would such a performance uptick vastly exceed any current x86 competition in the server space in terms of per-core performance, it would be enough to match the current best high-performance desktop chips from AMD and Intel today (Though we have to remember it’ll compete against next-gen Zen3 Milan and Willow Cove Sapphire Rapids products).
Neoverse N2 is Perseus – Continues the PPA Focus
Alongside the Neoverse V1 platform, we’ve seen a roadmap insertion that previously wasn’t there. The Perseus design will become the Neoverse N2, and will be the effective product-positioning successor to the N1. This new CPU IP represents a 40% IPC uplift compared to the N1, however still maintains the same design philosophy of maximising performance within the lowest power and smallest area.
It can be a bit confusing when it comes to the microarchitectural generations that we’re talking about here, so I made a graph to illustrate what we could call generational siblings between Arm’s mobile, and server CPU IP:
Although this is just a general rough outline of Arm’s products, the important thing to note that there’s similarities between generations of Cortex and Neoverse products as they’ve being developed in tandem at similar moments in time during their design. The Neoverse N1 was developed in conjunction with the Cortex-A76, and thus the two microarchitectures can be regarded as sibling designs as they share a lot of similarities.
The Neoverse V1 can be regarded as a sibling design to the Cortex-X1, likely sharing a lot of the supersized core structures that had been developed for these two flagship CPUs.
The Neoverse N2 is a bit more special as it represents the sibling design to a next-generation Cortex-A core which is the follow-up to the A78. Arm says they’ll be licensing out this “Perseus” design by the end of the year and that customers already are engaging on beta RTL – we’re likely to hear more about this generation of products at next year’s TechDay event. The N2 would be lagging behind the V1 by one year and subsequently it'll take more time to see this in products.
As a note, all of the above designs are all based in Austin and can be regarded as in the same microarchitecture family that had been started off with the Cortex-A76. If I’m not mistaken, next-generation “Poseidon” designs will be on a fresh new microarchitecture started by Arm’s Sophia-Antipolis design team – although Arm does note that there’s a lot more collaboration and blur between the different teams nowadays. Here Arm already notes a +30% IPC uplift for this generation of designs, likely to hit products in 2023.
An Undisclosed Architecture with SVE: Armv9?
One very notable characteristic of both the Neoverse V1 and N2 are the fact that these now support SVE (Scalable Vector Extensions), with the V1 having two native 256-bit pipelines and the N2 being a 2x128-bit design. The advantage of SVE over other SIMD ISAs is the fact that code written in it can scale with the varying execution width of a microarchitecture, something that’s just not possible with today’s Neon or AVX SIMD instructions.
Fujitsu’s A64FX chip and custom core microarchitecture had been to date the only CPU announced and available with SVE, meaning the V1 and N2 will be Arm’s first own designs actually implementing SVE.
Today’s announcements around this part of the V1 and N2 CPUs raised more questions than it answered, as the company wasn’t willing to disclose whether this support referred to the first-generation SVE instruction set, or whether they already supported SVE2.
In fact, the company wouldn’t confirm even the base architecture of the designs, whether this were Armv8 designs or one of the subsequent iterations. This is extremely unusual for the company as it’s traditionally transparent on such basic aspects of their IPs.
What I think is happening here is that the V1 and N2 might be both Armv9 designs, and the company will be publicly revealing the new ISA iteration sometime between today’s announcement and mid next year at the latest – of course this is all just my own interpretation of the situation as Arm refused to comment on the topic.
Update: Actually it does seem that Arm had already publicly upstreamed the initial compiler entries to GCC for Zeus back in June, confirming that at least the Neoverse V1 is an Armv8.4+SVE(1) design. I still think the N2 might be a v9+SVE2 design.
At the end of the day, what we end up are two extremely compelling new microarchitectures that significantly push Arm’s positioning in the infrastructure market. The Neoverse N2 is an obvious design that focuses on Arm’s PPA metrics, and the company sees customers designing products that are primarily focused on “scale-out” workloads that requite a lot of CPU cores. Here we could see designs up to 128 cores.
The Neoverse V1 will see designs with lesser core-counts as the CPUs are just bigger and more power hungry. Arm sees the 64-96 range being what’s most likely to be adopted by licensees. These are the premier products that will be going against the best of what Intel and AMD have to offer- and if the performance projections pan out (as they usually do for Arm), then we’re in for a brutally competitive fight unlike we’ve seen before.
The first publicly known design confirmed to employ the new Neoverse V1 cores is SiPearl’s “Rhea” chip that looks to feature 72 cores in a 7nm TSMC process node. Ampere’s “Siryn” design would also be a candidate for applying the V1 microarchitecture, targeted for a 2022 release on TSMC’s 5nm node.
Today’s announcement has been more of a teaser or unveiling, with the company planning to go into more details about the architecture and microarchitectures of the designs at a later date. Arm's DevSummit is scheduled for October 6-8th - and might be where we'll hear a bit more about the new architecture.Last edited by ssk; 23 Sep 2020, 18:19:35.Comment
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ผมอ่านผ่านๆๆอยู่ครับในเว็บฮาร์ดแวร์
ชื่อแอมแปร์์์นึกถึึง. Nvi.dia เอามากๆComment
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ผมมองว่าอนาคตชิพประมวลผลจะมุ่งไปสู่ APU และ unified memory ครับ คือ CPU กับ GPU เข้าถึงหน่วยความจำก้อนเดียวกัน และสามารถเข้าไปอ่านเขียนแรมได้ทุกๆ address ที่มีในเครื่อง เหมือนกับในคอนโซลในตอนนี้
ซึ่งหากทำได้สำเร็จจะได้ชิพประมวลผลที่ทั้งประมวลผลได้เร็วและเข้าถึงแรมได้มหาศาล (มีประโยชน์กว่ามีการ์ดจอ Titan แรม 128GB ซะอีก) การประมวลผลข้อมูลขนาดใหญ่จะสะดวกขึ้นมาก การเขียนโปรแกรมก็ทำได้ง่ายเหมือนเขียนโปรแกรมปกติ ไม่ต้องยุ่งยากใช้ภาษา CUDA, OpenCL เพื่อเรียกใช้พลัง GPU โดยตรง เรื่องนี้ต้องอาศัยแรงหนุนจากหลายทาง ทั้งเรื่องเทคโนโลยี RAM, I/O และฝั่ง OS, Compiler และซอฟแวร์ด้วย (จริงๆมันคือสวรรค์ของฝั่งซอฟแวร์เลย)
ในแง่ที่ว่ามานี้ ฝั่ง x86 และ Arm ยังไม่มีใครได้เปรียบเสียเปรียบกัน ต้องดูต่อไปว่าใครจะไปถึงจุดหมายก่อนครับ
ใครอ่านได้ลองไปอ่านดูครับ น่าสนใจมาก "Unified Memory: จิ๊กซอว์ตัวสุดท้ายของการเขียนโปรแกรม GPU"
https://www.nextplatform.com/2019/01...amming-puzzle/Comment
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อย่าลืม ตัวอื่นด้วยครับท่านนกแสก
ก็มี. I.b.m. power 10. ริคส์ตัวแม่อีกตัว
หวังว่ามาใช้พลัง radeon.instinc.
มัั่งปกติคบแต่เขียว
อาร์มรุกฝั่ง server. ส่วน รืคส์วี
ก็รุกตลาด arm. คอมฝังตัว
หวีงว่ากููููููเกิ้ลเปิดรับเข้าโครงการแอนดรอยด์Last edited by micronz; 24 Sep 2020, 23:44:57.Comment
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Samsung Confirms Custom CPU Development Cancellation
AMD-SAMSUNG CUSTOMS CHIP สงสัยจะแท้งรึเปล่า จากข่าวนี้ เหตุผลเรื่องการใช้พลังงาน อย่างว่าของมันแรงมันเลยกินไฟ
กับ ARM กำลังจะออก NEXT CORE มันเลยยกเลิกไป เพราะน่าจะไปใช่ CORE ใหม่แทน คงต้องให้ Apple กับ MS ดัน ARM Cloundbook ให้ติดตลาดไปซักพักก่อน อาจหันมาทำกันใหม่
by Andrei Frumusanu on November 4, 2019 9:00 AM EST
The fate of Samsung's custom CPU development efforts has been making the rounds of the rumour mill for almost a month, and now we finally have confirmation from Samsung that the company has stopped further development work on its custom Arm architecture CPU cores. This public confirmation comes via Samsung’s HR department, which last week filled an obligatory notice letter with the Texas Workforce Commission, warning about upcoming layoffs of Samsung’s Austin R&D Center CPU team and the impending termination of their custom CPU work.
The CPU project, said currently to be around 290 team members large, started off sometime in 2012 and has produced the custom ARMv8 CPU microarchitectures from the Exynos M1 in the Exynos 8890 up to the latest Exynos M5 in the upcoming Exynos 990.
Over the years, Samsung’s custom CPU microarchitectures had a tough time in differentiating themselves from Arm’s own Cortex designs, never being fully competitive in any one metric. The Exynos-M3 Meerkat cores employed in the Exynos 9810 (Galaxy S9), for example, ended up being more of a handicap to the SoC due to its poor energy efficiency. Even the CPU project itself had a rocky start, as originally the custom microarchitecture was meant to power Samsung’s custom Arm server SoCs before the design efforts were redirected towards mobile use.
In a response to Android Authority, Samsung confirmed the choice was based on business and competitive merits. A few years ago, Samsung had told us that custom CPU development was significantly more expensive than licensing Arm’s CPU IP. Indeed, it’s a very large investment to make in the face of having the up-hill battle of not only to designing a core matching Arm’s IP, but actually beating them.
Beyond the custom CPU’s competitiveness, the cancellation likely is tied to both Samsung’s and Arm’s future CPU roadmaps and timing. Following Deimos (Cortex-A77) and Hercules (Cortex-A78?), Arm is developing a new high-performance CPU on the new ARMv9 architecture, and we expect a major new v9 little core to also accompany the Matterhorn design. It’s likely that Samsung would have had to significantly ramp up R&D to be able to intercept Arm's ambitious design, if even possible at all given the area, performance, and efficiency gaps.
In practice, the end result is bittersweet. On one hand, the switch back to Cortex-A CPUs in future Exynos flagship SoCs should definitely benefit SLSI’s offerings, hopefully helping the division finally achieve SoC design wins beyond Samsung’s own Mobile division – or dare I hope, even fully winning a Samsung Galaxy design instead of only being a second-source alongside Qualcomm.
On the other hand, it means there’s one less custom CPU development team in the industry which is unfortunate. The Exynos 990 with the M5 cores will be the last we’ll see of Samsung’s custom CPU cores in the near future, as we won't be seeing the in-development M6. M6 was an SMT microarchitecture, which frankly quite perplexed me as a mobile targeted CPU – I definitely would have wanted to see how that would have played out, just from an academic standpoint.
The SARC and ACL activities in Austin and San Jose will continue as Samsung’s SoC, AI, and custom GPU teams are still active, the latter project which seems to be continuing alongside the new AMD GPU collaboration and IP licensing for future Exynos SoCs.
Last edited by ssk; 29 Sep 2020, 09:27:43.Comment
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น่าเสียดายจริงๆๆ นะครับข่าวชัวร์ไม้ครับว่ายกเลิกแท้งไปละComment
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ตามนี้ครับ AMD ยังทำอยู่ แต่ลดคนและยกเลิกงาน CUSTOM ของตัวเอง ในอณาคตยังไม่แน่นอนว่าจะยังไง เพราะเห็นบอกThe SARC and ACL activities in Austin and San Jose will continue as Samsung’s SoC, AI, and custom GPU teams are still active, the latter project which seems to be continuing alongside the new AMD GPU collaboration and IP licensing for future Exynos SoCs.
ตัวนี้แผนเสร็จ 2021/22 และต้องดู NVIDIA ARM อีกทีละมั้งครับ
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TSMC Ramps Up 3 nm Node Production
TSMC พร้อมที่จะผลิต NODE 3 nm ตามแผนในปี 2022 แล้วนะครับ ไม่เลื่อนเหมือน INTEL 7 nm แน่นอนแล้วล่ะครับ
by AleksandarK Yesterday, 13:28 Discuss (16 Comments)
TSMC has had quite a good time recently. They are having all of their capacity fully booked and the development of new semiconductor nodes is going good. Today, thanks to the report of DigiTimes, we have found out that TSMC is ramping up the production lines to prepare for 3 nm high-volume manufacturing. The 3 nm node is expected to enter HVM in 2022, which is not that far away. In the beginning, the new node is going to be manufactured on 55.000 wafers of 300 mm size, and it is expected to reach as much as 100.000 wafers per month output by 2023. With the accelerated purchase of EUV machines, TSMC already has all of the equipment required for the manufacturing of the latest node. We are waiting to see more details on the 3 nm node as we approach its official release.Comment
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ใช่ครับข่าวแปลไทยก็อัพเดท แผนสามนาโน และพัฒนา 2 นาโนเมตรแล้ว
ไม่รู้อินเทลจะแย่งคิวได้ไหม เพราะประกาศลูกค้าหลัก ยังเป้น แอปเปิ้ล เอเอ้มดี มีเดียเทค เช่นกันLast edited by micronz; 29 Sep 2020, 20:36:13.Comment
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ส่วนผมมีอัพเดทให้ฝั่งมือถือนิดหน่อย
https://www.gsmarena.com/xiaomi_redmi_note_10-10247.php
เรดมี่โน้ต 10 เปิดตัวที่จีนไปแล้ว จะรอไม่ไหวแล้วเนี่ยเข้าไทยราคาประหยัด
7200-8000 ได้แรม 6 gb
ชิพเซ้ตที่รอคอย มีเดียเทค ไดเม็นซิตี้ 5G
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ผมทนรอตัวนี้อยู่นี่แหละครับComment
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https://9to5linux.com/first-look-at-...gl2G-Y0Tltwslg
ลีนุกส์ยอดนิยมอีกตัวก็ใช้ตัวนี้อยู่บอกตรงๆๆว่าประทับใจในความเสถียรและความเบา
เตรียมออกเวอร์ชั่น `Deepin เพิ่มมาอีก DE เป้นดิสโทรที่เล่นแรม DDR3 8`gb ได้เยี่ยมมากๆๆ
แต่ถ้าใครใช้ตัวสองคอร์แบบ คอร์ทูดูโอ ลงตัวแม่ Arch จะเบากว่ามากๆๆ
Last edited by micronz; 1 Oct 2020, 06:46:20.Comment
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