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Finaly if all else fails AMD's Bulldozer has an aggressive cache system.
L0 cache: 4 kB (8-way associative) trace cache for each thread (or core)
L1 cache: 16 kB (4-way) data cache per core 1 cycle latency and 128 kB (4-way) instruction cache per module
L2 cache: 2 MB (8-way) per module (shared between two cores), full-speed
L3 cache: 8 MB shared between all cores, the L3 cache with a latency of 24 cycles will be able to serve up to 2 requests per (NB) clock cycle simultaneously and transfer data with 16B/clock to each of the reciepients.
L4 cache: AMD has also announced that all Black Editions and Opterons models will come with 32/64MB L4 cache made possible through chip stacking.But now a bit more about the details. The instruction fetch unit (IFU) fetches code from the L1 instruction cache (at 32 Bytes/cycle).
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