* Prefetch directly into L1 cache as opposed to L2 cache with K8 family
* 32-way set associative L3 victim cache sized at least 2 MiB, shared between processing cores on a single die (each with 512 KiB of independent exclusive L2 cache), with a sharing-aware replacement policy.
* Extensible L3 cache design, with 6 MiB planned for 45 nm process node, with the chips codenamed Shanghai.
* Prefetch directly into L1 cache as opposed to L2 cache with K8 family
* 32-way set associative L3 victim cache sized at least 2 MiB, shared between processing cores on a single die (each with 512 KiB of independent exclusive L2 cache), with a sharing-aware replacement policy.
* Extensible L3 cache design, with 6 MiB planned for 45 nm process node, with the chips codenamed Shanghai.
* Prefetch directly into L1 cache as opposed to L2 cache with K8 family
* 32-way set associative L3 victim cache sized at least 2 MiB, shared between processing cores on a single die (each with 512 KiB of independent exclusive L2 cache), with a sharing-aware replacement policy.
* Extensible L3 cache design, with 6 MiB planned for 45 nm process node, with the chips codenamed Shanghai.
Comment